View 6810_313576.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
6809 AND 6810
DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
The A6809- and A6810- devices combine 10-bit CMOS shift registers, accompanying data latches and control circuitry with bipolar sourcing outputs and pnp active pull downs. Designed primarily to drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings also allow these devices to be used in many other peripheral power driver applications. The A6809- and A6810- feature an increased data input rate (compared with the older UCN/UCQ5810-F) and a controlled output slew rate. The A6809xLW and A6810xLW are identical except for pinout. The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical serial-data input rates are up to 33 MHz. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are available as the A6811- (12 bits), A6812- (20 bits), and A6818- (32 bits). The A6809- and A6810- output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate reduces electromagnetic noise, which is an important consideration in systems that include telecommunications and/or microprocessors and to meet government emissions regulations. For inter-digit blanking, all output drivers can be disabled and all sink drivers turned on with a BLANKING input high. The pnp active pull-downs will sink at least 2.5 mA. Th A6810- is available in three temperature ranges for optimum performance in commercial (suffix S-), industrial (suffix E-), or automotive (suffix K-) applications; package styles are provided for throughhole DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimumarea surface-mount PLCC (suffix -EP). The A6809- is provided in the commercial or industrial temperature ranges and in the SOIC package (suffixes SLW or ELW) only. Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow all devices to source 25 mA from all outputs continuously at 85C or more than 5 mA over the maximum operating temperature range.
Data Sheet 26182.124A
A6810xA
OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4
1 2 3 LATCHES 4 5 6 7 8 9 VDD ST CLK REGISTER REGISTER LATCHES
18 17 16 VBB 15 14 BLNK 13 12 11 10
OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25C
Logic Supply Voltage, VDD ................... 7.0 V Driver Supply Voltage, V BB ................... 60 V Continuous Output Current Range, IOUT ......................... -40 mA to +15 mA Input Voltage Range, VIN ....................... -0.3 V to VDD + 0.3 V Package Power Dissipation, PD ........................................ See Graph Operating Temperature Range, TA (Suffix `E-') .................. -40C to +85C (Suffix `K-') ................ -40C to +125C (Suffix `S-') .................. -20C to +85C Storage Temperature Range, TS ............................... -55C to +125C
Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high static electrical charges.
FEATURES
s Controlled Output Slew Rate s Low Output-Saturation Voltages s High-Speed Data Storage s Low-Power CMOS Logic s 60 V Minimum and Latches Output Breakdown s Improved Replacements s High Data Input Rate for TL4810-, UCN5810-, s PNP Active Pull-Downs and UCQ5810- Complete part number includes a suffix to identify operating temperature range (E-, K-, or S-) and package type (-A, -EP, or -LW). Always order by complete part number, e.g., A6810SLW .
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
TYPICAL OUTPUT DRIVER
V BB
TYPICAL INPUT CIRCUIT
V DD
OUTN
IN
Dwg. EP-021-19
A6809ELW and A6809SLW
Dwg. EP-010-5
OUT 8 OUT 7 OUT 6 CLOCK GROUND NO CONNECTION LOGIC SUPPLY STROBE OUT 5 OUT 4
1 2 3 LATCHES 4 5 6 7 8 9 10 NC VDD ST REGISTER LATCHES CLK REGISTER V
20 19 NC 18 17 16 15 BLNK 14 13 12 11
OUT 9 OUT 10 NO CONNECTION SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3
CLOCK NC GROUND LOGIC SUPPLY STROBE 4 5 6 7 8 V DD ST CLK
OUT 6
A6810xEP
OUT10 20 19 2 1
3
18 LATCHES REGISTER V BB 17 16 REGISTER 15 LATCHES BLNK 14
BB
SERIAL DATA OUT LOAD SUPPLY NC SERIAL DATA IN BLANKING
12
10
11
OUT 5
OUT1
13
9
Dwg. PP-029-9
Dwg. PP-059
A6810xLW
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
2.5
SUFFIX 'EP', R JA = 59C/W
OUT 8 OUT 7 OUT 6 CLOCK GROUND LOGIC SUPPLY STROBE OUT 5 OUT 4 NO CONNECTION
1 2 3 LATCHES 4 5 6 7 8 9 10 NC VDD ST CLK REGISTER REGISTER LATCHES
20 19 18 VBB 17 16 BLNK 15 14 13 12 NC 11
OUT 9 OUT 10 SERIAL DATA OUT LOAD SUPPLY SERIAL DATA IN BLANKING OUT 1 OUT 2 OUT 3 NO CONNECTION
2.0
SUFFIX 'A', R JA = 60C/W
1.5
1.0
0.5
SUFFIX 'LW', R JA = 70C/W
0 25 50 75 100 125 AMBIENT TEMPERATURE IN C 150
Dwg. PP-029-2
Dwg. GP-024-1
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1998, Allegro MicroSystems, Inc.
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
FUNCTIONAL BLOCK DIAGRAM
CLOCK SERIAL DATA IN STROBE V DD LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR LOAD SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 IN Blanklng
Output Contents I1 I2 I3 ... IN-1 I N
R1 R2 R3 ... X X X ...
RN-1 RN PN-1 PN X X L H P1 P2 P3 ... PN-1 PN L L L ... L L
P1 P2 P3 ...
PN-1 PN
X
X
...
P = Present State
R = Previous State
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25C (A6809SLW & A6810S-) or over operating temperature range (A6809ELW, A6810E-, & A6810K-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V Characteristic Output Leakage Current Output Voltage Symbol I CEX VOUT(1) VOUT(0) Output Pull-Down Current Input Voltage IOUT(0) VIN(1) VIN(0) Input Current IIN(1) IIN(0) Input Clamp Voltage Serial Data Output Voltage VIK VOUT(1) VOUT(0) Maximum Clock Frequency Logic Supply Current fc IDD(1) IDD(0) Load Supply Current IBB(1) IBB(0) Blanking-to-Output Delay tdis(BQ) t en(BQ) Strobe-to-Output Delay tp(STH-QL) tp(STH-QH) Output Fall Time Output Rise Time Output Slew Rate tf tr dV/dt All Outputs High All Outputs Low All Outputs High, No Load All Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF RL = 2.3 k, C L 30 pF IOUT = 200 A VIN = VDD VIN = 0 V IIN = -200 A IOUT = -200 A IOUT = 200 A Test Conditions VOUT = 0 V IOUT = -25 mA IOUT = 1 mA VOUT = 5 V to VBB Mln. -- 57.5 -- 2.5 2.2 -- -- -- -- 2.8 -- 10 -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 <-0.01 -0.8 3.05 0.15 33 0.25 0.25 1.5 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 Max. -15 -- 1.5 -- -- 1.1 1.0 -1.0 -1.5 -- 0.3 -- 0.75 0.75 3.0 20 2.0 3.0 2.0 3.0 12 12 20 -- Limits @ VDD = 5 V Min. -- 57.5 -- 2.5 3.3 -- -- -- -- 4.5 -- 10 -- -- -- -- -- -- -- -- 2.4 2.4 4.0 -- Typ. <-0.1 58.3 1.0 5.0 -- -- <0.01 Max. -15 -- 1.5 -- -- 1.7 1.0 Units A V V mA V V A A V V V MHz mA mA mA A s s s s s s V/s ns
<-0.01 -1.0 -0.8 4.75 0.15 33 0.3 0.3 1.5 0.2 0.7 1.8 0.7 1.8 -- -- -- 50 -1.5 -- 0.3 -- 1.0 1.0 3.0 20 2.0 3.0 2.0 3.0 12 12 20 --
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal. Typical data is is for design information only and is at TA = +25C.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V DD and Ground)
C CLOCK A SERIAL DATA IN DATA
50%
B
50%
t p(CH-SQX) SERIAL DATA OUT D STROBE
50% 50%
DATA E
BLANKING
LOW = ALL OUTPUTS ENABLED t p(STH-QH) t p(STH-QL)
90%
OUT N
DATA
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED) BLANKING
50%
t dis(BQ) t en(BQ) OUT N tr
90% 10%
tf
DATA
A. Data Active Time Before Clock Pulse (Data Set-Up Time), tsu(D) ......................................... 25 ns B. Data Active Time After Clock Pulse (Data Hold Time), th(D) ............................................... 25 ns C. Clock Pulse Width, tw(CH) ............................................... 50 ns D. Time Between Clock Activation and Strobe, t su(C) ....... 100 ns E. Strobe Pulse Width, tw(STH) ............................................. 50 ns NOTE - Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable.
Dwg. WP-030
Information present at any register is transferred to the respective latch when the STROBE is high (serial-toparallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
A6810EA, A6810KA, & A6810SA
Dimensions in Inches (controlling dimensions)
18 10 0.014 0.008
0.430 0.280 0.240
MAX
0.300
BSC
1
0.070 0.045
0.100 0.920 0.880
BSC
9
0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-18A in
Dimensions in Millimeters (for reference only)
0.355 0.204
18
10
10.92 7.11 6.10
MAX
7.62
BSC
1
1.77 1.15
2.54 23.37 22.35
BSC
9
0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-18A mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
A6810EEP, A6810KEP, & A6810SEP
Dimensions in Inches (controlling dimensions)
13 0.021 0.013 0.169 0.141 14 0.395 0.385 0.032 0.026
INDEX AREA
9
8
0.050 0.169 0.141
BSC
0.356 0.350 18 4
19 0.020
MIN
20
1
2
3
0.356 0.350 0.395 0.385
Dwg. MA-005-20A in
0.180 0.165
Dimensions in Millimeters (for reference only)
13 0.533 0.331 4.29 3.58 14 10.03 9.78 0.812 0.661
INDEX AREA
9
8
1.27 4.29 3.58
BSC
9.042 8.890 18 4
19 0.51
MIN
20
1
2
3
9.042 8.890 10.03 9.78
Dwg. MA-005-20A mm
4.57 4.20
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
6809 AND 6810 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS
A6809ELW, A6809SLW, A6810ELW, A6810KLW, & A6810SLW
Dimensions in Inches (for reference only)
20 11 0.0125 0.0091
0.2992 0.2914
0.419 0.394
0.050 0.016 0.020 0.013
1
2
3 0.5118 0.4961
0.050
BSC
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-20 in
Dimensions in Millimeters (controlling dimensions)
20 11 0.32 0.23
7.60 7.40
10.65 10.00
1.27 0.40 0.51 0.33
1
2
3 13.00 12.60
1.27
BSC
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-20 mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

▲Up To Search▲

Price & Availability of 6810

	To Download 6810 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .